Central Processing Unit and Main Memory Unit

This section connects the five-unit model to an instruction actually running. You will identify CPU registers, calculate memory addresses and bus throughput, build simple arithmetic from gates, and explain how caches and parallel execution improve performance. Keep the distinction between an address, an instruction and an operand in view throughout.

The control unit coordinates transfers and execution. The ALU performs arithmetic, comparisons and logical operations. Registers provide small, fast working locations. The instruction decoder interprets an instruction’s operation code; the CPU’s clock provides timing events that organize these activities.

CPU registers ↗ · 2 questions have distinct roles. Similar names do not mean that two registers store the same kind of value.

A stack is last-in, first-out storage. Push saves an item and pop retrieves the most recently saved item. The stack’s growth direction and whether SP points to an occupied or next-free location depend on the architecture; neither changes the register’s role.

Clock period is the reciprocal of clock frequency. A 100 MHz clock has a period of 1/(100×10⁶) s = 10 ns. An instruction may take more than one clock cycle, and different designs do different amounts of work per cycle. For a simplified instruction stream:

CPU time = instruction count × average cycles per instruction ÷ clock frequency

For 2 million instructions, average CPI 3 and a 200 MHz clock, time = (2×10⁶×3)/(200×10⁶) = 0.03 s. Comparing clock rates alone would ignore both instruction count and CPI.

An address bus identifies a location, a data bus transfers the value, and a control bus carries signals such as read/write and completion. Internal buses connect parts of a CPU; external/system, memory, I/O and expansion buses connect broader parts of a system. Serial links send bits sequentially; parallel buses transfer multiple bits at once. A physical data width need not equal the processor’s advertised word width.

Bus transfer rate ↗ · 1 question depends on useful transfers per second, not just the input clock:

bytes/s = (data bits per transfer ÷ 8) × (input clock cycles/s ÷ input cycles per transfer)

A 32-bit bus using a 50 MHz input clock and two input cycles per transfer carries 4 × 25×10⁶ = 100 MB/s in a decimal theoretical model. Waiting, arbitration and protocol overhead may reduce useful throughput. DDR-style signaling can use both clock edges, but apply that multiplier only when the transfer rules specify it. Historical PCI uses a shared parallel bus; PCI Express uses serial lanes. Their versions, lane counts and protocols matter more than the superficial “serial versus parallel” label.

Semiconductor memory stores state in electronic circuits. MOS/CMOS and bipolar technologies describe device construction; they do not by themselves tell us whether a finished memory is volatile. For the functional distinction, ask how it retains bits and whether power or refresh is needed.

“Random access” describes reaching locations without sequentially passing through all earlier ones. It does not mean random contents. Volatile means ordinary stored state is lost when its sustaining power is removed. A flash-based SSD is semiconductor memory, yet is not volatile main DRAM. Cache does not replace the need to understand this distinction.

Main memory has storage cells, address-selection circuitry and read/write circuitry. A read sends an address, selects the corresponding location and returns its stored value. A write supplies both an address and the new value, with control signals identifying the operation. The address identifies a location; it is not the data stored there.

With a address bits, a simple address space has 2^a addressable locations. Capacity also depends on the amount stored at each location. Sixteen address bits and one byte per location give 65,536 bytes, or 64 KiB. If each address selects a two-byte word, the same number of addresses covers 128 KiB. Check the addressing unit rather than assuming one address always means one byte.

Memory modules combine chips into an appropriate width and number of locations. Historical SIMM and DIMM names refer to module arrangements; adding a module requires matching the system’s supported technology and organization. A removable flash memory card increases storage capacity, not automatically the CPU’s directly usable main RAM.

Worked example. One chip organized as 1M × 8 stores 2²⁰ locations of eight bits, or 1 MiB. Four chips operating side by side can supply a 32-bit word at each location: 1M × 32 = 4 MiB. Two banks of that arrangement double the location count and require eight chips in total. Distinguish widening each access from adding more addresses.

A machine instruction contains an opcode identifying the operation and fields identifying operands, registers or addressing information. Its binary layout is defined by the instruction-set architecture. An operand field might be a literal value, a register number or part of a memory address; interpreting every operand field as a final address is a mistake.

Data-transfer instructions load, store or move values. Arithmetic instructions add or subtract; logical instructions combine or shift bits; comparison and conditional-branch instructions select a path; call and return instructions manage procedure flow. A branch changes which instruction address is used next. An I/O instruction or memory-mapped device access controls an external device under the system’s rules.

The number of explicit operands varies. An accumulator machine can have an implicit operand; a register-register instruction may name two sources and a destination. “One instruction” is not necessarily “one memory access” or “one clock cycle.”

Suppose PC=200 and a two-byte instruction at that address means “add the value at address 900 to register R1.” Fetch puts the instruction word into IR and advances the sequential PC to 202 under this model. Decode identifies the addition and addressing mode. Operand fetching obtains memory[900]; the ALU adds it to R1; write-back stores the result. A taken branch would select a different next PC.

The PC and IR therefore contain different kinds of information even during the same instruction. The instruction decoder consumes instruction fields from IR, not the data value produced by an earlier arithmetic operation. Condition flags may change after execution and guide a later branch.

The effective address (EA) is the address actually used to access an operand. Let A be an instruction’s address field, M[x] the value stored at memory address x, R an index register and B a base register. Register contents and address fields must use consistent units.

Indexed access supports repeated elements; base-relative access supports locating a program or data region; PC-relative access supports nearby branches or data references. The PC reference may be defined as the current or next instruction address, so use the problem’s convention. Likewise, an array index may need scaling by element size before it becomes a byte displacement.

Check the indirection. If A=40 and M[40]=700, the immediate operand is 40, a direct load returns 700, and an indirect load returns the value held at address 700. The same number appears in the instruction, but the results need not be equal.

An interrupt or exception causes the processor to suspend its current sequence and run a handler. An external device completion or timer can generate an external interrupt. A running instruction can cause a synchronous exception such as an invalid operation. Names and exact classifications vary by architecture; the essential point is that the processor needs a controlled way to enter a handler and resume safely.

The system saves the necessary PC and status, selects a handler and enters an appropriate privileged execution context. The handler services the event, acknowledges it as required, restores state and returns. An interrupt does not mean that the suspended program starts again at its first instruction.

Interrupt priority ↗ · 1 question determines which eligible handler can run when several events compete. With nested interrupts permitted, a higher-priority handler can preempt a lower-priority one. The lower-priority handler then continues its unfinished work; it does not run its entire original duration again. Masked events may wait until enabled.

Timeline example. A low-priority handler starts at time 0 and needs 3 ms. A high-priority event arrives at 1 ms and needs 0.5 ms. The low-priority handler has completed 1 ms, so 2 ms remain. It resumes at 1.5 and finishes at 3.5 ms. Total handler CPU time is still 3.5 ms if switching overhead is ignored. Mark exact time boundaries before counting how much time the main program receives.

Boolean logic works with two states. AND is true when both inputs are true; inclusive OR is true when at least one is true; NOT inverts a state. XOR is true when two inputs differ. NAND negates AND, and NOR negates OR. A bubble on a circuit symbol means inversion at that connection.

Logic gates and equivalent circuits ↗ · 5 questions can be compared by evaluating every input combination, rather than judging a drawing’s appearance.

Useful identities include A AND 1=A, A OR 0=A, A AND 0=0, A OR 1=1, and A XOR A=0. De Morgan’s laws move a negation across an entire group: NOT(A AND B)=(NOT A) OR (NOT B), and NOT(A OR B)=(NOT A) AND (NOT B). Change both the operation and the inputs’ negations; changing only one produces a different function.

These are alternative circuit descriptions with the same truth values. Parentheses identify the group that an operation or negation applies to.

A two-input multiplexer (MUX) selects one data input. With select S, output Y=(NOT S AND I₀) OR (S AND I₁). If I₀=A and I₁=NOT A, the output is A when S=0 and inverted A when S=1: exactly A XOR S. This is a function derived from the connections, not a rule that every MUX is an XOR gate.

To derive a circuit from a truth table, write one AND term for each row where output=1, using an input or its negation to match that row; OR the terms together. Then simplify with identities and verify the resulting truth table. Naming intermediate outputs makes complemented connections easier to follow.

A half adder adds two one-bit inputs. Its sum is A XOR B, and its carry is A AND B. For 1+1, the result is binary 10: sum 0 and carry 1. A full adder also accepts an incoming carry C_in:

sum = A XOR B XOR C_in
carry = (A AND B) OR (C_in AND (A XOR B))

For A=1, B=0 and C_in=1, sum=0 and carry=1. Connecting stages produces a multi-bit adder; in a simple ripple-carry arrangement a later stage waits for an earlier carry. A flip-flop stores a bit of state, unlike a purely combinational gate whose output depends only on its present inputs. Registers combine state-holding elements.

Two’s-complement subtraction reuses addition: A−B=A+(NOT B)+1 within a chosen width. An ALU can select normal or complemented operand bits and use the carry-in for the added one. Separate logic detects conditions such as zero and signed overflow. An adder’s final carry is not automatically the signed-overflow flag.

Registers, cache, main memory and auxiliary storage form a hierarchy balancing speed, capacity and cost. Temporal locality favors recently reused data; spatial locality favors nearby addresses. A cache keeps copies of memory blocks so many accesses can avoid a slower level. A miss continues to the next level; it is not a failure to retain the original file.

For hit probability h and complete hit/miss path times, average access time = h×T_hit+(1−h)×T_miss. If the given miss time is an additional penalty, instead add it to the lookup time with its miss probability. The existing Memory hierarchy & cache focus lesson develops both timing models and preserves its three reviewed questions.

Write-through updates the next level when the cache is written; it simplifies keeping that level current but creates write traffic. Write-back marks a cache block dirty and writes it to the next level when required, often on eviction. A dirty block is modified, not defective. Buffers and coherence mechanisms are important in actual systems, so do not assume every cache uses the same write policy.

Memory interleaving places successive locations in different banks so operations can overlap. If a bank needs several cycles before accepting another access, alternating independent banks can improve the sustained transfer rate. Four banks do not necessarily make every single access four times faster: latency, access patterns, conflicts and bus capacity still matter.

A pipeline overlaps stages of different instructions. It improves throughput when the stages can proceed smoothly; it need not shorten the latency of one instruction. With three one-cycle stages—fetch F, decode D and execute E—four independent instructions take six cycles instead of twelve in an ideal non-overlapped model:

This original timing diagram shows filling and draining the pipeline. A data dependency, shared hardware resource or branch can insert stalls or flush work. A super-pipeline splits work into more stages; it can reduce the work per stage but increases the number of stages affected by a disruption.

RISC emphasizes a relatively regular instruction organization, often with simpler load/store operations and fixed-length formats. CISC includes more complex instruction forms and often variable-length encodings. Hard-wired control implements control decisions with circuits; microprogrammed control sequences smaller internal control operations. These are design approaches, not a guarantee that one named family always finishes a program faster. Real implementations can combine techniques.

Superscalar hardware finds opportunities to issue multiple instructions in parallel; VLIW makes parallel-operation groupings more explicit in compiler-generated long instruction words. Out-of-order execution can perform ready operations ahead of blocked ones while preserving the program’s required architectural behavior.

Multicore places multiple processing cores on a chip. Independent tasks can run concurrently, but shared memory, coordination and serial parts of a program limit speedup. If 25% of execution is inherently serial and 75% can be divided perfectly across four cores, the ideal total time relative to one core is 0.25+0.75/4=0.4375, giving speedup about 2.29—not four.

Use the technique that addresses the actual bottleneck. A deeper pipeline does not increase disk rotation speed, and more cores do not remove a dependency that requires one calculation’s result before another can begin.